1. Field of the Invention
The present invention relates to charge trapping memory devices, including charge trapping memory device used in a NAND flash configuration.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate. Charge trapping memory cells use dielectric charge trapping material that does not cause cell-to-cell interference to the degree encountered with floating gate technology, and can be applied for higher density flash memory.
The typical charge trapping memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a stack of dielectric material including a tunneling dielectric layer, the charge storage layer, and a blocking dielectric layer. According to the early conventional designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunneling dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed a silicon oxide (O), and the gate comprises polysilicon (S). The SONOS device is programmed by electron tunneling using one of a number of well-known biasing technologies, and erased by hole tunneling or electron de-trapping.
One focus of investigation for charge trapping memory cells has been on NAND style architectures. See, for example, Shin et al., “A Highly Reliable SONOS-type NAND Flash Memory Cell with Al2O3 or Top Oxide,” IEDM, 2003 (MANOS); and Shin et al., “A Novel NAND-type MONOS Memory using 63 nm Process Technology for a Multi-Gigabit Flash EEPROMs”, IEEE 2005.
In a NAND style architecture, the memory cells are arranged in series so that current used for reading data passes through a string of memory cells. This path through the cells limits the amount of current and the speed at which the read operation can be accomplished.
The present inventors have been involved in the development a charge trapping memory using bandgap engineered charge trapping technology, referred to as BE-SONOS. A variety of embodiments of BE-SONOS memory cells can be seen in U.S. Pat. No. 7,426,140 B2 by Lue, and in U.S. Patent Application Publication No. US2007/0029625 by Lue et al. BE-SONOS is characterized by the ability to block charge tunneling at relatively low electric fields, while enabling very efficient tunneling at moderately high electric fields. BE-SONOS also has very good endurance and reliability characteristics. BE-SONOS technology has been proposed for finFET non-volatile memory as well in U.S. Patent Application Publication No. US 2008/0087946 by Hsu et al., and U.S. Patent Application Publication No. US 2008/0087942 by Hsu et al.
One problem with charge-trapping devices arises because the memory windows are generally shifted upward toward positive VT as compared with the floating gate NAND flash. This causes difficulty in circuit design, since a higher pass gate voltage is required. Techniques are used to push the erased state memory window negative, such as by using high work function gates and other technologies. However, the tendency to operate with higher threshold levels remains a problem.
It is desirable to provide a dielectric charge trapping cell improves NAND architecture performance, and can be readily manufactured.